1. Field of the Invention
The present invention relates to a recorded information reproducing apparatus for reproducing information recorded on an optical disc and, more particularly, to a technique for improving an apparatus for reproducing recorded information including a waveform equalization circuit for compensating for a distortion of a waveform of a read signal that originates in attenuation characteristics in a high frequency band which are frequency characteristics of an optical system of the reproducing apparatus.
2. Description of the Related Art
FIG. 1 illustrates a schematic configuration of a CD (compact disc) player as an apparatus for reproducing recorded information as described above.
Referring to FIG. 1, a CD 3 which is an optical disc driven for rotation by a spindle motor 2 based on a rotation control signal supplied from a spindle servo circuit 9 at a speed of rotation which provides a predetermined linear velocity. A pick-up 1 receives a beam reflected by the CD 3 when the CD 3 is irradiated with a light beam and generates a read signal having a signal level in accordance with the quantity of the received light. A head amplifier 4 supplies an amplified read signal obtained by performing desired amplification on such a read signal to an analog equalizer 5 as a waveform equalization circuit 5.
The analog equalizer 5 performs waveform compensation on this amplified read signal to provide frequency characteristics such that a predetermined high frequency band of the amplified read signal is enhanced and supplies the resultant signal to a comparator 6. Specifically, the analog equalizer 5 increases the amplitude of high frequency components of a read signal by force to compensate for a decrease in the amplitude of such high frequency components which is said to occur in an optical reproduction system such as a CD player.
The comparator 6 compares the signal level of a read signal which has been subjected to waveform compensation by such an analog equalizer 5 with a predetermined reference voltage and generates a binary signal in accordance with the result of the comparison.
A clock signal generation circuit 7 has a configuration of a so-called PLL (phase locked loop) circuit, generates a clock signal which is phase-locked to signal edges of such a binary signal, and supplies it to a sampling circuit 8.
The sampling circuit 8 samples the binary signal at timing in accordance with such a clock signal and sequentially outputs resultant signals as reproduction digital signals.
Meanwhile, such a CD player includes a position detection circuit 10 which outputs a position detection signal indicative of the position of the pick-up 1 in the radial direction of the disc, for example, by optically or mechanically reading a scale (a scale indicating positions in the radial direction) provided on a slider base carrying a slider transporting the pick-up 1 in the radial direction of the disc and includes a frequency detection circuit 11 which detects the speed of rotation (rotational frequency) of the spindle motor 2 that carries the CD 3 and for outputting a frequency detection signal. Each of the detection signals from the position detection circuit 10 and frequency detection circuit 11 is supplied to a control CPU 12.
The control CPU 12 controls an access operation to move the pick-up to a predetermined position to be read on the disc in the radial direction thereof based on the supplied position detection signal and sets a speed of rotation for the disc corresponding to such a predetermined radial position on the CD 3 which is a disc recorded on a CLV (constant linear velocity) basis (hereinafter referred to as "CLV disc") in the spindle servo circuit 9 based on the frequency detection signal.
Meanwhile, a spindle motor 2 for rotating heavy a load like a disc is generally slow in response because of inertial force of the load. Therefore, according to algorithm which waits for the spindle motor 2 to reach a predetermined speed of rotation after a seek operation before proceeding to an operation of reproducing recorded information (decoding operation), a great amount of time is spent before the information recorded in a desired reading position is reproduced. Under such circumstances, algorithm for high speed access is recently employed which proceeds to the operation of reproducing recorded information when the pick-up 1 has moved to a desired reading position as a result of an access operation without waiting for the spindle motor 2 to reach a predetermined speed of rotation at the position on the disc in the radial direction thereof.
Based on the speed of rotation of the spindle motor 2 supplied by the frequency detection circuit 11 at the time when transition from the operation of moving the pick-up 2 to the desired reading position to the reproduction operation takes place, i.e., based on the frequency detection signal indicative of the speed of rotation of the CD 3, the CPU 12 sets the oscillation frequency of a VCO (voltage controlled oscillator), which is not shown, in the clock generation circuit 7 and sets band characteristics of the analog equalizer 5.
After the oscillation frequency of the VCO is initialized by the CPU 12, the clock generation circuit 7 performs phase comparison between signal edges of the binary signal based on the read signal from the CD 3 and a clock signal generated by the VCO and generates a clock signal which is phase-locked to the signal edges of the binary signal. Since the speed of rotation of the spindle motor 2 varies until it is subjected to control for steady rotation after reaching a predetermined speed of rotation, the frequency of the binary signal varies in accordance with the variation of the speed of rotation. However, once phase-locking is achieved, the clock signal generation circuit 7 is able to continue to generate a clock signal that follows the variation of the binary signal provided that the range of the variation of the binary signal is within the band width which the PLL can follow. Therefore, the CPU 12 needs only to initialize the oscillation frequency of the clock signal based on the speed of rotation of the spindle motor (the frequency detection signal supplied by the frequency detection circuit 11) at the time when it is brought into the phase-locked state.
Meanwhile, the analog equalizer 5 is constituted by an analog integrated circuit which is a combination of variable conductance amplifiers and MOS capacitor arrays in a multiplicity of stages and has band characteristics, i.e., high frequency band components, that vary depending on conductance set by the CPU 12. During the period in which the speed of rotation of the spindle motor 2 is varied for high speed access as described above, the frequency of the amplified read signal input through the head amplifier 4 also varies depending on the speed of rotation. During such a transition period, the CPU 12 continuously monitors the frequency detection signal and continues to set the conductance so that the band characteristics of the analog equalizer 5 change depending on the change in the frequency of the detection signal.
As described above, the analog equalizer 5 is configured such that its band characteristics vary depending on the conductance set by the CPU 12. Thus, for reproduction of recorded information during a period in which the speed of rotation of a disc varies as a result of high speed access or the like, the CPU 12 must repeatedly set the conductance so that the analog equalizer 5 has band characteristics in accordance with the speed of rotation by continually holding control thereon, which has resulted in a problem that complicated processing must be carried out by the CPU 12.